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constants-arm64.h File Reference
#include <inttypes.h>
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Namespaces

 v8
 
 v8::internal
 

Macros

#define __STDC_FORMAT_MACROS
 
#define REGISTER_CODE_LIST(R)
 
#define INSTRUCTION_FIELDS_LIST(V_)
 
#define SYSTEM_REGISTER_FIELDS_LIST(V_, M_)
 
#define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2)
 
#define DECLARE_INSTRUCTION_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1)   DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2)
 
#define NOTHING(A, B)
 
#define ADD_SUB_OP_LIST(V)
 
#define ADD_SUB_IMMEDIATE(A)
 
#define ADD_SUB_SHIFTED(A)
 
#define ADD_SUB_EXTENDED(A)
 
#define LOAD_STORE_PAIR_OP_LIST(V)
 
#define LOAD_STORE_PAIR(A, B, C)   A##_##B = C
 
#define LOAD_STORE_PAIR_POST_INDEX(A, B, C)   A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B
 
#define LOAD_STORE_PAIR_PRE_INDEX(A, B, C)   A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B
 
#define LOAD_STORE_PAIR_OFFSET(A, B, C)   A##_##B##_off = LoadStorePairOffsetFixed | A##_##B
 
#define LOAD_STORE_OP_LIST(V)
 
#define LOAD_STORE_UNSCALED(A, B, C, D)   A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D
 
#define LOAD_STORE(A, B, C, D)   A##B##_##C = D
 
#define LOAD_STORE_POST_INDEX(A, B, C, D)   A##B##_##C##_post = LoadStorePostIndexFixed | D
 
#define LOAD_STORE_PRE_INDEX(A, B, C, D)   A##B##_##C##_pre = LoadStorePreIndexFixed | D
 
#define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D)   A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D
 
#define LOAD_STORE_REGISTER_OFFSET(A, B, C, D)   A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D
 

Enumerations

enum  Condition {
  kNoCondition = -1, eq = 0 << 28, ne = 1 << 28, cs = 2 << 28,
  cc = 3 << 28, mi = 4 << 28, pl = 5 << 28, vs = 6 << 28,
  vc = 7 << 28, hi = 8 << 28, ls = 9 << 28, ge = 10 << 28,
  lt = 11 << 28, gt = 12 << 28, le = 13 << 28, al = 14 << 28,
  kSpecialCondition = 15 << 28, kNumberOfConditions = 16, hs = cs, lo = cc,
  eq = 0 << 28, ne = 1 << 28, hs = cs, lo = cc,
  mi = 4 << 28, pl = 5 << 28, vs = 6 << 28, vc = 7 << 28,
  hi = 8 << 28, ls = 9 << 28, ge = 10 << 28, lt = 11 << 28,
  gt = 12 << 28, le = 13 << 28, al = 14 << 28, nv = 15,
  no_condition = -1, overflow = 0, no_overflow = 1, below = 2,
  above_equal = 3, equal = 4, not_equal = 5, below_equal = 6,
  above = 7, negative = 8, positive = 9, parity_even = 10,
  parity_odd = 11, less = 12, greater_equal = 13, less_equal = 14,
  greater = 15, carry = below, not_carry = above_equal, zero = equal,
  not_zero = not_equal, sign = negative, not_sign = positive, kNoCondition = -1,
  overflow = 0, no_overflow = 1, Uless = 2, Ugreater_equal = 3,
  equal = 4, not_equal = 5, Uless_equal = 6, Ugreater = 7,
  negative = 8, positive = 9, parity_even = 10, parity_odd = 11,
  less = 12, greater_equal = 13, less_equal = 14, greater = 15,
  ueq = 16, nue = 17, cc_always = 18, carry = below,
  not_carry = above_equal, zero = equal, eq = 0 << 28, not_zero = not_equal,
  ne = 1 << 28, nz = not_equal, sign = negative, not_sign = positive,
  mi = 4 << 28, pl = 5 << 28, hi = 8 << 28, ls = 9 << 28,
  ge = 10 << 28, lt = 11 << 28, gt = 12 << 28, le = 13 << 28,
  hs = cs, lo = cc, al = 14 << 28, cc_default = kNoCondition,
  no_condition = -1, overflow = 0, no_overflow = 1, below = 2,
  above_equal = 3, equal = 4, not_equal = 5, below_equal = 6,
  above = 7, negative = 8, positive = 9, parity_even = 10,
  parity_odd = 11, less = 12, greater_equal = 13, less_equal = 14,
  greater = 15, always = 16, never = 17, carry = below,
  not_carry = above_equal, zero = equal, not_zero = not_equal, sign = negative,
  not_sign = positive, last_condition = greater
}
 
enum  FlagsUpdate { SetFlags = 1, LeaveFlags = 0 }
 
enum  StatusFlags {
  NoFlag = 0, NFlag = N_mask, ZFlag = Z_mask, CFlag = C_mask,
  VFlag = V_mask, NZFlag = NFlag | ZFlag, NCFlag = NFlag | CFlag, NVFlag = NFlag | VFlag,
  ZCFlag = ZFlag | CFlag, ZVFlag = ZFlag | VFlag, CVFlag = CFlag | VFlag, NZCFlag = NFlag | ZFlag | CFlag,
  NZVFlag = NFlag | ZFlag | VFlag, NCVFlag = NFlag | CFlag | VFlag, ZCVFlag = ZFlag | CFlag | VFlag, NZCVFlag = NFlag | ZFlag | CFlag | VFlag,
  FPEqualFlag = ZCFlag, FPLessThanFlag = NFlag, FPGreaterThanFlag = CFlag, FPUnorderedFlag = CVFlag
}
 
enum  Shift {
  NO_SHIFT = -1, LSL = 0 << 5, LSR = 1 << 5, ASR = 2 << 5,
  ROR = 3 << 5
}
 
enum  Extend {
  NO_EXTEND = -1, UXTB = 0, UXTH = 1, UXTW = 2,
  UXTX = 3, SXTB = 4, SXTH = 5, SXTW = 6,
  SXTX = 7
}
 
enum  SystemHint {
  NOP = 0, YIELD = 1, WFE = 2, WFI = 3,
  SEV = 4, SEVL = 5
}
 
enum  BarrierDomain { OuterShareable = 0, NonShareable = 1, InnerShareable = 2, FullSystem = 3 }
 
enum  BarrierType { BarrierOther = 0, BarrierReads = 1, BarrierWrites = 2, BarrierAll = 3 }
 
enum  SystemRegister { NZCV, FPCR }
 
enum  GenericInstrField { SixtyFourBits = 0x80000000, ThirtyTwoBits = 0x00000000, FP32 = 0x00000000, FP64 = 0x00400000 }
 
enum  PCRelAddressingOp {
  PCRelAddressingFixed = 0x10000000, PCRelAddressingFMask = 0x1F000000, PCRelAddressingMask = 0x9F000000, ADR = PCRelAddressingFixed | 0x00000000,
  ADRP = PCRelAddressingFixed | 0x80000000
}
 
enum  AddSubOp {
  AddSubOpMask = 0x60000000, AddSubSetFlagsBit = 0x20000000, ADD = 4 << 21, ADDS = ADD | AddSubSetFlagsBit,
  SUB = 2 << 21, SUBS = SUB | AddSubSetFlagsBit
}
 
enum  AddSubImmediateOp { AddSubImmediateFixed = 0x11000000, AddSubImmediateFMask = 0x1F000000, AddSubImmediateMask = 0xFF000000 }
 
enum  AddSubShiftedOp { AddSubShiftedFixed = 0x0B000000, AddSubShiftedFMask = 0x1F200000, AddSubShiftedMask = 0xFF200000 }
 
enum  AddSubExtendedOp { AddSubExtendedFixed = 0x0B200000, AddSubExtendedFMask = 0x1F200000, AddSubExtendedMask = 0xFFE00000 }
 
enum  AddSubWithCarryOp {
  AddSubWithCarryFixed = 0x1A000000, AddSubWithCarryFMask = 0x1FE00000, AddSubWithCarryMask = 0xFFE0FC00, ADC_w = AddSubWithCarryFixed | ADD,
  ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits, ADC = 5 << 21, ADCS_w = AddSubWithCarryFixed | ADDS, ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,
  SBC_w = AddSubWithCarryFixed | SUB, SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits, SBC = 6 << 21, SBCS_w = AddSubWithCarryFixed | SUBS,
  SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits
}
 
enum  LogicalOp {
  LogicalOpMask = 0x60200000, NOT = 0x00200000, AND = 0 << 21, BIC = 14 << 21,
  ORR = 12 << 21, ORN = ORR | NOT, EOR = 1 << 21, EON = EOR | NOT,
  ANDS = 0x60000000, BICS = ANDS | NOT
}
 
enum  LogicalImmediateOp {
  LogicalImmediateFixed = 0x12000000, LogicalImmediateFMask = 0x1F800000, LogicalImmediateMask = 0xFF800000, AND_w_imm = LogicalImmediateFixed | AND,
  AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits, ORR_w_imm = LogicalImmediateFixed | ORR, ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits, EOR_w_imm = LogicalImmediateFixed | EOR,
  EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits, ANDS_w_imm = LogicalImmediateFixed | ANDS, ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
}
 
enum  LogicalShiftedOp {
  LogicalShiftedFixed = 0x0A000000, LogicalShiftedFMask = 0x1F000000, LogicalShiftedMask = 0xFF200000, AND_w = LogicalShiftedFixed | AND,
  AND_x = LogicalShiftedFixed | AND | SixtyFourBits, AND_shift = AND_w, BIC_w = LogicalShiftedFixed | BIC, BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits,
  BIC_shift = BIC_w, ORR_w = LogicalShiftedFixed | ORR, ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits, ORR_shift = ORR_w,
  ORN_w = LogicalShiftedFixed | ORN, ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits, ORN_shift = ORN_w, EOR_w = LogicalShiftedFixed | EOR,
  EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits, EOR_shift = EOR_w, EON_w = LogicalShiftedFixed | EON, EON_x = LogicalShiftedFixed | EON | SixtyFourBits,
  EON_shift = EON_w, ANDS_w = LogicalShiftedFixed | ANDS, ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits, ANDS_shift = ANDS_w,
  BICS_w = LogicalShiftedFixed | BICS, BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits, BICS_shift = BICS_w
}
 
enum  MoveWideImmediateOp {
  MoveWideImmediateFixed = 0x12800000, MoveWideImmediateFMask = 0x1F800000, MoveWideImmediateMask = 0xFF800000, MOVN = 0x00000000,
  MOVZ = 0x40000000, MOVK = 0x60000000, MOVN_w = MoveWideImmediateFixed | MOVN, MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits,
  MOVZ_w = MoveWideImmediateFixed | MOVZ, MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits, MOVK_w = MoveWideImmediateFixed | MOVK, MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits
}
 
enum  BitfieldOp {
  BitfieldFixed = 0x13000000, BitfieldFMask = 0x1F800000, BitfieldMask = 0xFF800000, SBFM_w = BitfieldFixed | 0x00000000,
  SBFM_x = BitfieldFixed | 0x80000000, SBFM = SBFM_w, BFM_w = BitfieldFixed | 0x20000000, BFM_x = BitfieldFixed | 0xA0000000,
  BFM = BFM_w, UBFM_w = BitfieldFixed | 0x40000000, UBFM_x = BitfieldFixed | 0xC0000000, UBFM = UBFM_w
}
 
enum  ExtractOp {
  ExtractFixed = 0x13800000, ExtractFMask = 0x1F800000, ExtractMask = 0xFFA00000, EXTR_w = ExtractFixed | 0x00000000,
  EXTR_x = ExtractFixed | 0x80000000, EXTR = EXTR_w
}
 
enum  UnconditionalBranchOp {
  UnconditionalBranchFixed = 0x14000000, UnconditionalBranchFMask = 0x7C000000, UnconditionalBranchMask = 0xFC000000, B = 1 << 22,
  BL = UnconditionalBranchFixed | 0x80000000
}
 
enum  UnconditionalBranchToRegisterOp {
  UnconditionalBranchToRegisterFixed = 0xD6000000, UnconditionalBranchToRegisterFMask = 0xFE000000, UnconditionalBranchToRegisterMask = 0xFFFFFC1F, BR = UnconditionalBranchToRegisterFixed | 0x001F0000,
  BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, RET = UnconditionalBranchToRegisterFixed | 0x005F0000
}
 
enum  CompareBranchOp {
  CompareBranchFixed = 0x34000000, CompareBranchFMask = 0x7E000000, CompareBranchMask = 0xFF000000, CBZ_w = CompareBranchFixed | 0x00000000,
  CBZ_x = CompareBranchFixed | 0x80000000, CBZ = CBZ_w, CBNZ_w = CompareBranchFixed | 0x01000000, CBNZ_x = CompareBranchFixed | 0x81000000,
  CBNZ = CBNZ_w
}
 
enum  TestBranchOp {
  TestBranchFixed = 0x36000000, TestBranchFMask = 0x7E000000, TestBranchMask = 0x7F000000, TBZ = TestBranchFixed | 0x00000000,
  TBNZ = TestBranchFixed | 0x01000000
}
 
enum  ConditionalBranchOp { ConditionalBranchFixed = 0x54000000, ConditionalBranchFMask = 0xFE000000, ConditionalBranchMask = 0xFF000010, B_cond = ConditionalBranchFixed | 0x00000000 }
 
enum  SystemOp { SystemFixed = 0xD5000000, SystemFMask = 0xFFC00000 }
 
enum  SystemSysRegOp {
  SystemSysRegFixed = 0xD5100000, SystemSysRegFMask = 0xFFD00000, SystemSysRegMask = 0xFFF00000, MRS = SystemSysRegFixed | 0x00200000,
  MSR = SystemSysRegFixed | 0x00000000
}
 
enum  SystemHintOp { SystemHintFixed = 0xD503201F, SystemHintFMask = 0xFFFFF01F, SystemHintMask = 0xFFFFF01F, HINT = SystemHintFixed | 0x00000000 }
 
enum  ExceptionOp {
  ExceptionFixed = 0xD4000000, ExceptionFMask = 0xFF000000, ExceptionMask = 0xFFE0001F, HLT = ExceptionFixed | 0x00400000,
  BRK = ExceptionFixed | 0x00200000, SVC = ExceptionFixed | 0x00000001, HVC = ExceptionFixed | 0x00000002, SMC = ExceptionFixed | 0x00000003,
  DCPS1 = ExceptionFixed | 0x00A00001, DCPS2 = ExceptionFixed | 0x00A00002, DCPS3 = ExceptionFixed | 0x00A00003
}
 
enum  MemBarrierOp {
  MemBarrierFixed = 0xD503309F, MemBarrierFMask = 0xFFFFF09F, MemBarrierMask = 0xFFFFF0FF, DSB = MemBarrierFixed | 0x00000000,
  DMB = MemBarrierFixed | 0x00000020, ISB = MemBarrierFixed | 0x00000040
}
 
enum  LoadStoreAnyOp { LoadStoreAnyFMask = 0x0a000000, LoadStoreAnyFixed = 0x08000000 }
 
enum  LoadStorePairAnyOp { LoadStorePairAnyFMask = 0x3a000000, LoadStorePairAnyFixed = 0x28000000 }
 
enum  LoadStorePairOp { LoadStorePairMask = 0xC4400000, LoadStorePairLBit = 1 << 22 }
 
enum  LoadStorePairPostIndexOp { LoadStorePairPostIndexFixed = 0x28800000, LoadStorePairPostIndexFMask = 0x3B800000, LoadStorePairPostIndexMask = 0xFFC00000 }
 
enum  LoadStorePairPreIndexOp { LoadStorePairPreIndexFixed = 0x29800000, LoadStorePairPreIndexFMask = 0x3B800000, LoadStorePairPreIndexMask = 0xFFC00000 }
 
enum  LoadStorePairOffsetOp { LoadStorePairOffsetFixed = 0x29000000, LoadStorePairOffsetFMask = 0x3B800000, LoadStorePairOffsetMask = 0xFFC00000 }
 
enum  LoadStorePairNonTemporalOp {
  LoadStorePairNonTemporalFixed = 0x28000000, LoadStorePairNonTemporalFMask = 0x3B800000, LoadStorePairNonTemporalMask = 0xFFC00000, STNP_w = LoadStorePairNonTemporalFixed | STP_w,
  LDNP_w = LoadStorePairNonTemporalFixed | LDP_w, STNP_x = LoadStorePairNonTemporalFixed | STP_x, LDNP_x = LoadStorePairNonTemporalFixed | LDP_x, STNP_s = LoadStorePairNonTemporalFixed | STP_s,
  LDNP_s = LoadStorePairNonTemporalFixed | LDP_s, STNP_d = LoadStorePairNonTemporalFixed | STP_d, LDNP_d = LoadStorePairNonTemporalFixed | LDP_d
}
 
enum  LoadLiteralOp {
  LoadLiteralFixed = 0x18000000, LoadLiteralFMask = 0x3B000000, LoadLiteralMask = 0xFF000000, LDR_w_lit = LoadLiteralFixed | 0x00000000,
  LDR_x_lit = LoadLiteralFixed | 0x40000000, LDRSW_x_lit = LoadLiteralFixed | 0x80000000, PRFM_lit = LoadLiteralFixed | 0xC0000000, LDR_s_lit = LoadLiteralFixed | 0x04000000,
  LDR_d_lit = LoadLiteralFixed | 0x44000000
}
 
enum  LoadStoreUnscaledOffsetOp { LoadStoreUnscaledOffsetFixed = 0x38000000, LoadStoreUnscaledOffsetFMask = 0x3B200C00, LoadStoreUnscaledOffsetMask = 0xFFE00C00 }
 
enum  LoadStoreOp { LoadStoreOpMask = 0xC4C00000, LOAD_STORE_OP_LIST =(LOAD_STORE), PRFM = 0xC0800000 }
 
enum  LoadStorePostIndex { LoadStorePostIndexFixed = 0x38000400, LoadStorePostIndexFMask = 0x3B200C00, LoadStorePostIndexMask = 0xFFE00C00 }
 
enum  LoadStorePreIndex { LoadStorePreIndexFixed = 0x38000C00, LoadStorePreIndexFMask = 0x3B200C00, LoadStorePreIndexMask = 0xFFE00C00 }
 
enum  LoadStoreUnsignedOffset { LoadStoreUnsignedOffsetFixed = 0x39000000, LoadStoreUnsignedOffsetFMask = 0x3B000000, LoadStoreUnsignedOffsetMask = 0xFFC00000, PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM }
 
enum  LoadStoreRegisterOffset { LoadStoreRegisterOffsetFixed = 0x38200800, LoadStoreRegisterOffsetFMask = 0x3B200C00, LoadStoreRegisterOffsetMask = 0xFFE00C00, PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM }
 
enum  ConditionalCompareOp { ConditionalCompareMask = 0x60000000, CCMN = 0x20000000, CCMP = 0x60000000 }
 
enum  ConditionalCompareRegisterOp {
  ConditionalCompareRegisterFixed = 0x1A400000, ConditionalCompareRegisterFMask = 0x1FE00800, ConditionalCompareRegisterMask = 0xFFE00C10, CCMN_w = ConditionalCompareRegisterFixed | CCMN,
  CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN, CCMP_w = ConditionalCompareRegisterFixed | CCMP, CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP
}
 
enum  ConditionalCompareImmediateOp {
  ConditionalCompareImmediateFixed = 0x1A400800, ConditionalCompareImmediateFMask = 0x1FE00800, ConditionalCompareImmediateMask = 0xFFE00C10, CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN,
  CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN, CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP, CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP
}
 
enum  ConditionalSelectOp {
  ConditionalSelectFixed = 0x1A800000, ConditionalSelectFMask = 0x1FE00000, ConditionalSelectMask = 0xFFE00C00, CSEL_w = ConditionalSelectFixed | 0x00000000,
  CSEL_x = ConditionalSelectFixed | 0x80000000, CSEL = CSEL_w, CSINC_w = ConditionalSelectFixed | 0x00000400, CSINC_x = ConditionalSelectFixed | 0x80000400,
  CSINC = CSINC_w, CSINV_w = ConditionalSelectFixed | 0x40000000, CSINV_x = ConditionalSelectFixed | 0xC0000000, CSINV = CSINV_w,
  CSNEG_w = ConditionalSelectFixed | 0x40000400, CSNEG_x = ConditionalSelectFixed | 0xC0000400, CSNEG = CSNEG_w
}
 
enum  DataProcessing1SourceOp {
  DataProcessing1SourceFixed = 0x5AC00000, DataProcessing1SourceFMask = 0x5FE00000, DataProcessing1SourceMask = 0xFFFFFC00, RBIT = DataProcessing1SourceFixed | 0x00000000,
  RBIT_w = RBIT, RBIT_x = RBIT | SixtyFourBits, REV16 = DataProcessing1SourceFixed | 0x00000400, REV16_w = REV16,
  REV16_x = REV16 | SixtyFourBits, REV = DataProcessing1SourceFixed | 0x00000800, REV_w = REV, REV32_x = REV | SixtyFourBits,
  REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00, CLZ = 1 << 4, CLZ_w = CLZ, CLZ_x = CLZ | SixtyFourBits,
  CLS = DataProcessing1SourceFixed | 0x00001400, CLS_w = CLS, CLS_x = CLS | SixtyFourBits
}
 
enum  DataProcessing2SourceOp {
  DataProcessing2SourceFixed = 0x1AC00000, DataProcessing2SourceFMask = 0x5FE00000, DataProcessing2SourceMask = 0xFFE0FC00, UDIV_w = DataProcessing2SourceFixed | 0x00000800,
  UDIV_x = DataProcessing2SourceFixed | 0x80000800, UDIV = UDIV_w, SDIV_w = DataProcessing2SourceFixed | 0x00000C00, SDIV_x = DataProcessing2SourceFixed | 0x80000C00,
  SDIV = SDIV_w, LSLV_w = DataProcessing2SourceFixed | 0x00002000, LSLV_x = DataProcessing2SourceFixed | 0x80002000, LSLV = LSLV_w,
  LSRV_w = DataProcessing2SourceFixed | 0x00002400, LSRV_x = DataProcessing2SourceFixed | 0x80002400, LSRV = LSRV_w, ASRV_w = DataProcessing2SourceFixed | 0x00002800,
  ASRV_x = DataProcessing2SourceFixed | 0x80002800, ASRV = ASRV_w, RORV_w = DataProcessing2SourceFixed | 0x00002C00, RORV_x = DataProcessing2SourceFixed | 0x80002C00,
  RORV = RORV_w, CRC32B = DataProcessing2SourceFixed | 0x00004000, CRC32H = DataProcessing2SourceFixed | 0x00004400, CRC32W = DataProcessing2SourceFixed | 0x00004800,
  CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00, CRC32CB = DataProcessing2SourceFixed | 0x00005000, CRC32CH = DataProcessing2SourceFixed | 0x00005400, CRC32CW = DataProcessing2SourceFixed | 0x00005800,
  CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00
}
 
enum  DataProcessing3SourceOp {
  DataProcessing3SourceFixed = 0x1B000000, DataProcessing3SourceFMask = 0x1F000000, DataProcessing3SourceMask = 0xFFE08000, MADD_w = DataProcessing3SourceFixed | 0x00000000,
  MADD_x = DataProcessing3SourceFixed | 0x80000000, MADD = MADD_w, MSUB_w = DataProcessing3SourceFixed | 0x00008000, MSUB_x = DataProcessing3SourceFixed | 0x80008000,
  MSUB = MSUB_w, SMADDL_x = DataProcessing3SourceFixed | 0x80200000, SMSUBL_x = DataProcessing3SourceFixed | 0x80208000, SMULH_x = DataProcessing3SourceFixed | 0x80400000,
  UMADDL_x = DataProcessing3SourceFixed | 0x80A00000, UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000, UMULH_x = DataProcessing3SourceFixed | 0x80C00000
}
 
enum  FPCompareOp {
  FPCompareFixed = 0x1E202000, FPCompareFMask = 0x5F203C00, FPCompareMask = 0xFFE0FC1F, FCMP_s = FPCompareFixed | 0x00000000,
  FCMP_d = FPCompareFixed | FP64 | 0x00000000, FCMP = FCMP_s, FCMP_s_zero = FPCompareFixed | 0x00000008, FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008,
  FCMP_zero = FCMP_s_zero, FCMPE_s = FPCompareFixed | 0x00000010, FCMPE_d = FPCompareFixed | FP64 | 0x00000010, FCMPE_s_zero = FPCompareFixed | 0x00000018,
  FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018
}
 
enum  FPConditionalCompareOp {
  FPConditionalCompareFixed = 0x1E200400, FPConditionalCompareFMask = 0x5F200C00, FPConditionalCompareMask = 0xFFE00C10, FCCMP_s = FPConditionalCompareFixed | 0x00000000,
  FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000, FCCMP = FCCMP_s, FCCMPE_s = FPConditionalCompareFixed | 0x00000010, FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010,
  FCCMPE = FCCMPE_s
}
 
enum  FPConditionalSelectOp {
  FPConditionalSelectFixed = 0x1E200C00, FPConditionalSelectFMask = 0x5F200C00, FPConditionalSelectMask = 0xFFE00C00, FCSEL_s = FPConditionalSelectFixed | 0x00000000,
  FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000, FCSEL = FCSEL_s
}
 
enum  FPImmediateOp {
  FPImmediateFixed = 0x1E201000, FPImmediateFMask = 0x5F201C00, FPImmediateMask = 0xFFE01C00, FMOV_s_imm = FPImmediateFixed | 0x00000000,
  FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000
}
 
enum  FPDataProcessing1SourceOp {
  FPDataProcessing1SourceFixed = 0x1E204000, FPDataProcessing1SourceFMask = 0x5F207C00, FPDataProcessing1SourceMask = 0xFFFFFC00, FMOV_s = FPDataProcessing1SourceFixed | 0x00000000,
  FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000, FMOV = FMOV_s, FABS_s = FPDataProcessing1SourceFixed | 0x00008000, FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000,
  FABS = FABS_s, FNEG_s = FPDataProcessing1SourceFixed | 0x00010000, FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000, FNEG = FNEG_s,
  FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000, FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000, FSQRT = FSQRT_s, FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000,
  FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000, FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000, FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000, FRINTN = FRINTN_s,
  FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000, FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000, FRINTP = FRINTP_s, FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000,
  FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000, FRINTM = FRINTM_s, FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000, FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000,
  FRINTZ = FRINTZ_s, FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000, FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000, FRINTA = FRINTA_s,
  FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000, FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000, FRINTX = FRINTX_s, FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000,
  FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000, FRINTI = FRINTI_s
}
 
enum  FPDataProcessing2SourceOp {
  FPDataProcessing2SourceFixed = 0x1E200800, FPDataProcessing2SourceFMask = 0x5F200C00, FPDataProcessing2SourceMask = 0xFFE0FC00, FMUL = FPDataProcessing2SourceFixed | 0x00000000,
  FMUL_s = FMUL, FMUL_d = FMUL | FP64, FDIV = FPDataProcessing2SourceFixed | 0x00001000, FDIV_s = FDIV,
  FDIV_d = FDIV | FP64, FADD = FPDataProcessing2SourceFixed | 0x00002000, FADD_s = FADD, FADD_d = FADD | FP64,
  FSUB = FPDataProcessing2SourceFixed | 0x00003000, FSUB_s = FSUB, FSUB_d = FSUB | FP64, FMAX = FPDataProcessing2SourceFixed | 0x00004000,
  FMAX_s = FMAX, FMAX_d = FMAX | FP64, FMIN = FPDataProcessing2SourceFixed | 0x00005000, FMIN_s = FMIN,
  FMIN_d = FMIN | FP64, FMAXNM = FPDataProcessing2SourceFixed | 0x00006000, FMAXNM_s = FMAXNM, FMAXNM_d = FMAXNM | FP64,
  FMINNM = FPDataProcessing2SourceFixed | 0x00007000, FMINNM_s = FMINNM, FMINNM_d = FMINNM | FP64, FNMUL = FPDataProcessing2SourceFixed | 0x00008000,
  FNMUL_s = FNMUL, FNMUL_d = FNMUL | FP64
}
 
enum  FPDataProcessing3SourceOp {
  FPDataProcessing3SourceFixed = 0x1F000000, FPDataProcessing3SourceFMask = 0x5F000000, FPDataProcessing3SourceMask = 0xFFE08000, FMADD_s = FPDataProcessing3SourceFixed | 0x00000000,
  FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000, FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000, FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000, FMADD_d = FPDataProcessing3SourceFixed | 0x00400000,
  FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000, FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000, FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000
}
 
enum  FPIntegerConvertOp {
  FPIntegerConvertFixed = 0x1E200000, FPIntegerConvertFMask = 0x5F20FC00, FPIntegerConvertMask = 0xFFFFFC00, FCVTNS = FPIntegerConvertFixed | 0x00000000,
  FCVTNS_ws = FCVTNS, FCVTNS_xs = FCVTNS | SixtyFourBits, FCVTNS_wd = FCVTNS | FP64, FCVTNS_xd = FCVTNS | SixtyFourBits | FP64,
  FCVTNU = FPIntegerConvertFixed | 0x00010000, FCVTNU_ws = FCVTNU, FCVTNU_xs = FCVTNU | SixtyFourBits, FCVTNU_wd = FCVTNU | FP64,
  FCVTNU_xd = FCVTNU | SixtyFourBits | FP64, FCVTPS = FPIntegerConvertFixed | 0x00080000, FCVTPS_ws = FCVTPS, FCVTPS_xs = FCVTPS | SixtyFourBits,
  FCVTPS_wd = FCVTPS | FP64, FCVTPS_xd = FCVTPS | SixtyFourBits | FP64, FCVTPU = FPIntegerConvertFixed | 0x00090000, FCVTPU_ws = FCVTPU,
  FCVTPU_xs = FCVTPU | SixtyFourBits, FCVTPU_wd = FCVTPU | FP64, FCVTPU_xd = FCVTPU | SixtyFourBits | FP64, FCVTMS = FPIntegerConvertFixed | 0x00100000,
  FCVTMS_ws = FCVTMS, FCVTMS_xs = FCVTMS | SixtyFourBits, FCVTMS_wd = FCVTMS | FP64, FCVTMS_xd = FCVTMS | SixtyFourBits | FP64,
  FCVTMU = FPIntegerConvertFixed | 0x00110000, FCVTMU_ws = FCVTMU, FCVTMU_xs = FCVTMU | SixtyFourBits, FCVTMU_wd = FCVTMU | FP64,
  FCVTMU_xd = FCVTMU | SixtyFourBits | FP64, FCVTZS = FPIntegerConvertFixed | 0x00180000, FCVTZS_ws = FCVTZS, FCVTZS_xs = FCVTZS | SixtyFourBits,
  FCVTZS_wd = FCVTZS | FP64, FCVTZS_xd = FCVTZS | SixtyFourBits | FP64, FCVTZU = FPIntegerConvertFixed | 0x00190000, FCVTZU_ws = FCVTZU,
  FCVTZU_xs = FCVTZU | SixtyFourBits, FCVTZU_wd = FCVTZU | FP64, FCVTZU_xd = FCVTZU | SixtyFourBits | FP64, SCVTF = FPIntegerConvertFixed | 0x00020000,
  SCVTF_sw = SCVTF, SCVTF_sx = SCVTF | SixtyFourBits, SCVTF_dw = SCVTF | FP64, SCVTF_dx = SCVTF | SixtyFourBits | FP64,
  UCVTF = FPIntegerConvertFixed | 0x00030000, UCVTF_sw = UCVTF, UCVTF_sx = UCVTF | SixtyFourBits, UCVTF_dw = UCVTF | FP64,
  UCVTF_dx = UCVTF | SixtyFourBits | FP64, FCVTAS = FPIntegerConvertFixed | 0x00040000, FCVTAS_ws = FCVTAS, FCVTAS_xs = FCVTAS | SixtyFourBits,
  FCVTAS_wd = FCVTAS | FP64, FCVTAS_xd = FCVTAS | SixtyFourBits | FP64, FCVTAU = FPIntegerConvertFixed | 0x00050000, FCVTAU_ws = FCVTAU,
  FCVTAU_xs = FCVTAU | SixtyFourBits, FCVTAU_wd = FCVTAU | FP64, FCVTAU_xd = FCVTAU | SixtyFourBits | FP64, FMOV_ws = FPIntegerConvertFixed | 0x00060000,
  FMOV_sw = FPIntegerConvertFixed | 0x00070000, FMOV_xd = FMOV_ws | SixtyFourBits | FP64, FMOV_dx = FMOV_sw | SixtyFourBits | FP64
}
 
enum  FPFixedPointConvertOp {
  FPFixedPointConvertFixed = 0x1E000000, FPFixedPointConvertFMask = 0x5F200000, FPFixedPointConvertMask = 0xFFFF0000, FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000,
  FCVTZS_ws_fixed = FCVTZS_fixed, FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits, FCVTZS_wd_fixed = FCVTZS_fixed | FP64, FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64,
  FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000, FCVTZU_ws_fixed = FCVTZU_fixed, FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits, FCVTZU_wd_fixed = FCVTZU_fixed | FP64,
  FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64, SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000, SCVTF_sw_fixed = SCVTF_fixed, SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits,
  SCVTF_dw_fixed = SCVTF_fixed | FP64, SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64, UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000, UCVTF_sw_fixed = UCVTF_fixed,
  UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits, UCVTF_dw_fixed = UCVTF_fixed | FP64, UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64
}
 
enum  UnimplementedOp { UnimplementedFixed = 0x00000000, UnimplementedFMask = 0x00000000 }
 
enum  UnallocatedOp { UnallocatedFixed = 0x00000000, UnallocatedFMask = 0x00000000 }
 

Functions

 STATIC_ASSERT (sizeof(int)==sizeof(int32_t))
 
 STATIC_ASSERT (sizeof(long)==sizeof(int64_t))
 
 STATIC_ASSERT (sizeof(void *)==sizeof(int64_t))
 
 STATIC_ASSERT (sizeof(1)==sizeof(int32_t))
 
 STATIC_ASSERT (sizeof(1L)==sizeof(int64_t))
 
Condition InvertCondition (Condition cond)
 
Condition ReverseConditionForCmp (Condition cond)
 

Variables

const unsigned kInstructionSize = 4
 
const unsigned kInstructionSizeLog2 = 2
 
const unsigned kLiteralEntrySize = 4
 
const unsigned kLiteralEntrySizeLog2 = 2
 
const unsigned kMaxLoadLiteralRange = 1 * MB
 
const unsigned kNumberOfRegisters = 32
 
const unsigned kNumberOfFPRegisters = 32
 
const int kNumberOfCalleeSavedRegisters = 11
 
const int kFirstCalleeSavedRegisterIndex = 19
 
const int kNumberOfCalleeSavedFPRegisters = 8
 
const int kFirstCalleeSavedFPRegisterIndex = 8
 
const unsigned kJSCalleeSavedRegList = 0x03f80000
 
const unsigned kWRegSizeInBits = 32
 
const unsigned kWRegSizeInBitsLog2 = 5
 
const unsigned kWRegSize = kWRegSizeInBits >> 3
 
const unsigned kWRegSizeLog2 = kWRegSizeInBitsLog2 - 3
 
const unsigned kXRegSizeInBits = 64
 
const unsigned kXRegSizeInBitsLog2 = 6
 
const unsigned kXRegSize = kXRegSizeInBits >> 3
 
const unsigned kXRegSizeLog2 = kXRegSizeInBitsLog2 - 3
 
const unsigned kSRegSizeInBits = 32
 
const unsigned kSRegSizeInBitsLog2 = 5
 
const unsigned kSRegSize = kSRegSizeInBits >> 3
 
const unsigned kSRegSizeLog2 = kSRegSizeInBitsLog2 - 3
 
const unsigned kDRegSizeInBits = 64
 
const unsigned kDRegSizeInBitsLog2 = 6
 
const unsigned kDRegSize = kDRegSizeInBits >> 3
 
const unsigned kDRegSizeLog2 = kDRegSizeInBitsLog2 - 3
 
const int64_t kWRegMask = 0x00000000ffffffffL
 
const int64_t kXRegMask = 0xffffffffffffffffL
 
const int64_t kSRegMask = 0x00000000ffffffffL
 
const int64_t kDRegMask = 0xffffffffffffffffL
 
const int64_t kDSignBit = 63
 
const int64_t kDSignMask = 0x1L << kDSignBit
 
const int64_t kSSignBit = 31
 
const int64_t kSSignMask = 0x1L << kSSignBit
 
const int64_t kXSignBit = 63
 
const int64_t kXSignMask = 0x1L << kXSignBit
 
const int64_t kWSignBit = 31
 
const int64_t kWSignMask = 0x1L << kWSignBit
 
const int64_t kDQuietNanBit = 51
 
const int64_t kDQuietNanMask = 0x1L << kDQuietNanBit
 
const int64_t kSQuietNanBit = 22
 
const int64_t kSQuietNanMask = 0x1L << kSQuietNanBit
 
const int64_t kByteMask = 0xffL
 
const int64_t kHalfWordMask = 0xffffL
 
const int64_t kWordMask = 0xffffffffL
 
const uint64_t kXMaxUInt = 0xffffffffffffffffUL
 
const uint64_t kWMaxUInt = 0xffffffffUL
 
const int64_t kXMaxInt = 0x7fffffffffffffffL
 
const int64_t kXMinInt = 0x8000000000000000L
 
const int32_t kWMaxInt = 0x7fffffff
 
const int32_t kWMinInt = 0x80000000
 
const unsigned kFramePointerRegCode = 29
 
const unsigned kLinkRegCode = 30
 
const unsigned kZeroRegCode = 31
 
const unsigned kJSSPCode = 28
 
const unsigned kSPRegInternalCode = 63
 
const unsigned kRegCodeMask = 0x1f
 
const unsigned kByteSize = 8
 
const unsigned kByteSizeInBytes = kByteSize >> 3
 
const unsigned kHalfWordSize = 16
 
const unsigned kHalfWordSizeLog2 = 4
 
const unsigned kHalfWordSizeInBytes = kHalfWordSize >> 3
 
const unsigned kHalfWordSizeInBytesLog2 = kHalfWordSizeLog2 - 3
 
const unsigned kWordSize = 32
 
const unsigned kWordSizeLog2 = 5
 
const unsigned kWordSizeInBytes = kWordSize >> 3
 
const unsigned kWordSizeInBytesLog2 = kWordSizeLog2 - 3
 
const unsigned kDoubleWordSize = 64
 
const unsigned kDoubleWordSizeInBytes = kDoubleWordSize >> 3
 
const unsigned kQuadWordSize = 128
 
const unsigned kQuadWordSizeInBytes = kQuadWordSize >> 3
 
const unsigned kDoubleMantissaBits = 52
 
const unsigned kDoubleExponentBits = 11
 
const unsigned kFloatMantissaBits = 23
 
const unsigned kFloatExponentBits = 8
 
const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask
 
const int kSFOffset = 31
 
const int kBitfieldNOffset = 22
 
const int kHltBadCode = 0xbad
 

Macro Definition Documentation

#define __STDC_FORMAT_MACROS

Definition at line 41 of file constants-arm64.h.

#define ADD_SUB_EXTENDED (   A)
Value:
A##_w_ext = AddSubExtendedFixed | A, \
A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits

Definition at line 490 of file constants-arm64.h.

#define ADD_SUB_IMMEDIATE (   A)
Value:
A##_w_imm = AddSubImmediateFixed | A, \
A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits

Definition at line 468 of file constants-arm64.h.

#define ADD_SUB_OP_LIST (   V)
Value:
V(ADD), \
V(ADDS), \
V(SUB), \
V(SUBS)

Definition at line 458 of file constants-arm64.h.

#define ADD_SUB_SHIFTED (   A)
Value:
A##_w_shift = AddSubShiftedFixed | A, \
A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits

Definition at line 479 of file constants-arm64.h.

#define DECLARE_FIELDS_OFFSETS (   Name,
  HighBit,
  LowBit,
  unused_1,
  unused_2 
)
Value:
const int Name##_offset = LowBit; \
const int Name##_width = HighBit - LowBit + 1; \
const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit;

Definition at line 244 of file constants-arm64.h.

#define DECLARE_INSTRUCTION_FIELDS_OFFSETS (   Name,
  HighBit,
  LowBit,
  unused_1 
)    DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2)

Definition at line 248 of file constants-arm64.h.

#define INSTRUCTION_FIELDS_LIST (   V_)

Definition at line 142 of file constants-arm64.h.

#define LOAD_STORE (   A,
  B,
  C,
  D 
)    A##B##_##C = D

Definition at line 843 of file constants-arm64.h.

#define LOAD_STORE_OP_LIST (   V)
Value:
V(ST, RB, w, 0x00000000), \
V(ST, RH, w, 0x40000000), \
V(ST, R, w, 0x80000000), \
V(ST, R, x, 0xC0000000), \
V(LD, RB, w, 0x00400000), \
V(LD, RH, w, 0x40400000), \
V(LD, R, w, 0x80400000), \
V(LD, R, x, 0xC0400000), \
V(LD, RSB, x, 0x00800000), \
V(LD, RSH, x, 0x40800000), \
V(LD, RSW, x, 0x80800000), \
V(LD, RSB, w, 0x00C00000), \
V(LD, RSH, w, 0x40C00000), \
V(ST, R, s, 0x84000000), \
V(ST, R, d, 0xC4000000), \
V(LD, R, s, 0x84400000), \
V(LD, R, d, 0xC4400000)

Definition at line 809 of file constants-arm64.h.

#define LOAD_STORE_PAIR (   A,
  B,
  C 
)    A##_##B = C

Definition at line 746 of file constants-arm64.h.

#define LOAD_STORE_PAIR_OFFSET (   A,
  B,
  C 
)    A##_##B##_off = LoadStorePairOffsetFixed | A##_##B

Definition at line 776 of file constants-arm64.h.

#define LOAD_STORE_PAIR_OP_LIST (   V)
Value:
V(STP, w, 0x00000000), \
V(LDP, w, 0x00400000), \
V(LDPSW, x, 0x40400000), \
V(STP, x, 0x80000000), \
V(LDP, x, 0x80400000), \
V(STP, s, 0x04000000), \
V(LDP, s, 0x04400000), \
V(STP, d, 0x44000000), \
V(LDP, d, 0x44400000)

Definition at line 731 of file constants-arm64.h.

#define LOAD_STORE_PAIR_POST_INDEX (   A,
  B,
  C 
)    A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B

Definition at line 756 of file constants-arm64.h.

#define LOAD_STORE_PAIR_PRE_INDEX (   A,
  B,
  C 
)    A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B

Definition at line 766 of file constants-arm64.h.

#define LOAD_STORE_POST_INDEX (   A,
  B,
  C,
  D 
)    A##B##_##C##_post = LoadStorePostIndexFixed | D

Definition at line 855 of file constants-arm64.h.

#define LOAD_STORE_PRE_INDEX (   A,
  B,
  C,
  D 
)    A##B##_##C##_pre = LoadStorePreIndexFixed | D

Definition at line 866 of file constants-arm64.h.

#define LOAD_STORE_REGISTER_OFFSET (   A,
  B,
  C,
  D 
)    A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D

Definition at line 890 of file constants-arm64.h.

#define LOAD_STORE_UNSCALED (   A,
  B,
  C,
  D 
)    A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D

Definition at line 834 of file constants-arm64.h.

#define LOAD_STORE_UNSIGNED_OFFSET (   A,
  B,
  C,
  D 
)    A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D

Definition at line 878 of file constants-arm64.h.

#define NOTHING (   A,
  B 
)

Definition at line 250 of file constants-arm64.h.

#define REGISTER_CODE_LIST (   R)
Value:
R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \
R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \
R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \
R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)

Definition at line 136 of file constants-arm64.h.

#define SYSTEM_REGISTER_FIELDS_LIST (   V_,
  M_ 
)
Value:
/* NZCV */ \
V_(Flags, 31, 28, Bits, uint32_t) \
V_(N, 31, 31, Bits, bool) \
V_(Z, 30, 30, Bits, bool) \
V_(C, 29, 29, Bits, bool) \
V_(V, 28, 28, Bits, uint32_t) \
M_(NZCV, Flags_mask) \
\
/* FPCR */ \
V_(AHP, 26, 26, Bits, bool) \
V_(DN, 25, 25, Bits, bool) \
V_(FZ, 24, 24, Bits, bool) \
V_(RMode, 23, 22, Bits, FPRounding) \
M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)

Definition at line 226 of file constants-arm64.h.

Function Documentation

STATIC_ASSERT ( sizeof(int)  = =sizeof(int32_t))
STATIC_ASSERT ( sizeof(long)  = =sizeof(int64_t))
STATIC_ASSERT ( sizeof(void *)  = =sizeof(int64_t))
STATIC_ASSERT ( sizeof(1)  = =sizeof(int32_t))
STATIC_ASSERT ( sizeof(1L)  = =sizeof(int64_t))