40 using namespace v8::internal;
50 if (strcmp(compare_string, disasm_buffer.
start()) != 0) {
56 compare_string, disasm_buffer.
start());
67 CcTest::InitializeVM(); \
68 Isolate* isolate = CcTest::i_isolate(); \
69 HandleScope scope(isolate); \
70 byte *buffer = reinterpret_cast<byte*>(malloc(4*1024)); \
71 Assembler assm(isolate, buffer, 4*1024); \
79 #define COMPARE(asm_, compare_string) \
81 int pc_offset = assm.pc_offset(); \
82 byte *progcounter = &buffer[pc_offset]; \
84 if (!DisassembleAndCompare(progcounter, compare_string)) failure = true; \
90 #define VERIFY_RUN() \
92 V8_Fatal(__FILE__, __LINE__, "MIPS Disassembler tests failed.\n"); \
100 "00a62021 addu a0, a1, a2");
102 "016c5021 addu t2, t3, t4");
104 "00701021 addu v0, v1, s0");
107 "00a62023 subu a0, a1, a2");
109 "016c5023 subu t2, t3, t4");
111 "00701023 subu v0, v1, s0");
114 "00850018 mult a0, a1");
116 "014b0018 mult t2, t3");
118 "00430018 mult v0, v1");
121 "00850019 multu a0, a1");
123 "014b0019 multu t2, t3");
125 "00430019 multu v0, v1");
128 "0085001a div a0, a1");
130 "014b001a div t2, t3");
132 "0043001a div v0, v1");
135 "0085001b divu a0, a1");
137 "014b001b divu t2, t3");
139 "0043001b divu v0, v1");
143 "70a62002 mul a0, a1, a2");
145 "716c5002 mul t2, t3, t4");
147 "70701002 mul v0, v1, s0");
151 "24a40000 addiu a0, a1, 0");
153 "26307fff addiu s0, s1, 32767");
155 "256a8000 addiu t2, t3, -32768");
157 "2462ffff addiu v0, v1, -1");
160 "00a62024 and a0, a1, a2");
162 "02328024 and s0, s1, s2");
164 "016c5024 and t2, t3, t4");
166 "00661024 and v0, v1, a2");
169 "00a62025 or a0, a1, a2");
171 "02328025 or s0, s1, s2");
173 "016c5025 or t2, t3, t4");
175 "00661025 or v0, v1, a2");
178 "00a62026 xor a0, a1, a2");
180 "02328026 xor s0, s1, s2");
182 "016c5026 xor t2, t3, t4");
184 "00661026 xor v0, v1, a2");
187 "00a62027 nor a0, a1, a2");
189 "02328027 nor s0, s1, s2");
191 "016c5027 nor t2, t3, t4");
193 "00661027 nor v0, v1, a2");
196 "30a40001 andi a0, a1, 0x1");
198 "3062ffff andi v0, v1, 0xffff");
201 "34a40001 ori a0, a1, 0x1");
203 "3462ffff ori v0, v1, 0xffff");
206 "38a40001 xori a0, a1, 0x1");
208 "3862ffff xori v0, v1, 0xffff");
211 "3c040001 lui a0, 0x1");
213 "3c02ffff lui v0, 0xffff");
216 "00052000 sll a0, a1, 0");
218 "00118200 sll s0, s1, 8");
220 "000b5600 sll t2, t3, 24");
222 "000317c0 sll v0, v1, 31");
225 "00c52004 sllv a0, a1, a2");
227 "02518004 sllv s0, s1, s2");
229 "018b5004 sllv t2, t3, t4");
231 "03c31004 sllv v0, v1, fp");
234 "00052002 srl a0, a1, 0");
236 "00118202 srl s0, s1, 8");
238 "000b5602 srl t2, t3, 24");
240 "000317c2 srl v0, v1, 31");
243 "00c52006 srlv a0, a1, a2");
245 "02518006 srlv s0, s1, s2");
247 "018b5006 srlv t2, t3, t4");
249 "03c31006 srlv v0, v1, fp");
252 "00052003 sra a0, a1, 0");
254 "00118203 sra s0, s1, 8");
256 "000b5603 sra t2, t3, 24");
258 "000317c3 sra v0, v1, 31");
261 "00c52007 srav a0, a1, a2");
263 "02518007 srav s0, s1, s2");
265 "018b5007 srav t2, t3, t4");
267 "03c31007 srav v0, v1, fp");
271 "00252002 rotr a0, a1, 0");
273 "00318202 rotr s0, s1, 8");
275 "002b5602 rotr t2, t3, 24");
277 "002317c2 rotr v0, v1, 31");
280 "00c52046 rotrv a0, a1, a2");
282 "02518046 rotrv s0, s1, s2");
284 "018b5046 rotrv t2, t3, t4");
286 "03c31046 rotrv v0, v1, fp");
290 "0000000d break, code: 0x00000 (0)");
292 "00ff000d break, code: 0x3fc00 (261120)");
294 "03ff000d break, code: 0xffc00 (1047552)");
297 "00850030 tge a0, a1, code: 0x000");
299 "0211fff0 tge s0, s1, code: 0x3ff");
301 "00850031 tgeu a0, a1, code: 0x000");
303 "0211fff1 tgeu s0, s1, code: 0x3ff");
305 "00850032 tlt a0, a1, code: 0x000");
307 "0211fff2 tlt s0, s1, code: 0x3ff");
309 "00850033 tltu a0, a1, code: 0x000");
311 "0211fff3 tltu s0, s1, code: 0x3ff");
313 "00850034 teq a0, a1, code: 0x000");
315 "0211fff4 teq s0, s1, code: 0x3ff");
317 "00850036 tne a0, a1, code: 0x000");
319 "0211fff6 tne s0, s1, code: 0x3ff");
339 "00a6202a slt a0, a1, a2");
341 "0232802a slt s0, s1, s2");
343 "016c502a slt t2, t3, t4");
345 "0066102a slt v0, v1, a2");
347 "00a6202b sltu a0, a1, a2");
349 "0232802b sltu s0, s1, s2");
351 "016c502b sltu t2, t3, t4");
353 "0066102b sltu v0, v1, a2");
356 "28a40000 slti a0, a1, 0");
358 "2a307fff slti s0, s1, 32767");
360 "296a8000 slti t2, t3, -32768");
362 "2862ffff slti v0, v1, -1");
364 "2ca40000 sltiu a0, a1, 0");
366 "2e307fff sltiu s0, s1, 32767");
368 "2d6a8000 sltiu t2, t3, -32768");
370 "2c62ffff sltiu v0, v1, -1");
374 "00a6200a movz a0, a1, a2");
376 "0232800a movz s0, s1, s2");
378 "016c500a movz t2, t3, t4");
380 "0066100a movz v0, v1, a2");
382 "00a6200b movn a0, a1, a2");
384 "0232800b movn s0, s1, s2");
386 "016c500b movn t2, t3, t4");
388 "0066100b movn v0, v1, a2");
391 "00a52001 movt a0, a1, 1");
393 "02298001 movt s0, s1, 2");
395 "016d5001 movt t2, t3, 3");
397 "007d1001 movt v0, v1, 7");
399 "00a02001 movf a0, a1, 0");
401 "02308001 movf s0, s1, 4");
403 "01745001 movf t2, t3, 5");
405 "00781001 movf v0, v1, 6");
408 "70a42020 clz a0, a1");
410 "72f6b020 clz s6, s7");
412 "70621020 clz v0, v1");
417 "7ca4ffc4 ins a0, a1, 31, 1");
419 "7ef6ff84 ins s6, s7, 30, 2");
421 "7c62f804 ins v0, v1, 0, 32");
423 "7ca407c0 ext a0, a1, 31, 1");
425 "7ef60f80 ext s6, s7, 30, 2");
427 "7c62f800 ext v0, v1, 0, 32");
int InstructionDecode(v8::internal::Vector< char > buffer, byte *instruction)
bool DisassembleAndCompare(byte *pc, const char *compare_string)
#define COMPARE(asm_, compare_string)