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atomicops_internals_mips_gcc.h
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27 
28 // This file is an internal atomic implementation, use atomicops.h instead.
29 
30 #ifndef V8_ATOMICOPS_INTERNALS_MIPS_GCC_H_
31 #define V8_ATOMICOPS_INTERNALS_MIPS_GCC_H_
32 
33 #define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
34 
35 namespace v8 {
36 namespace internal {
37 
38 // Atomically execute:
39 // result = *ptr;
40 // if (*ptr == old_value)
41 // *ptr = new_value;
42 // return result;
43 //
44 // I.e., replace "*ptr" with "new_value" if "*ptr" used to be "old_value".
45 // Always return the old value of "*ptr"
46 //
47 // This routine implies no memory barriers.
48 inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
49  Atomic32 old_value,
50  Atomic32 new_value) {
51  Atomic32 prev, tmp;
52  __asm__ __volatile__(".set push\n"
53  ".set noreorder\n"
54  "1:\n"
55  "ll %0, %5\n" // prev = *ptr
56  "bne %0, %3, 2f\n" // if (prev != old_value) goto 2
57  "move %2, %4\n" // tmp = new_value
58  "sc %2, %1\n" // *ptr = tmp (with atomic check)
59  "beqz %2, 1b\n" // start again on atomic error
60  "nop\n" // delay slot nop
61  "2:\n"
62  ".set pop\n"
63  : "=&r" (prev), "=m" (*ptr), "=&r" (tmp)
64  : "Ir" (old_value), "r" (new_value), "m" (*ptr)
65  : "memory");
66  return prev;
67 }
68 
69 // Atomically store new_value into *ptr, returning the previous value held in
70 // *ptr. This routine implies no memory barriers.
71 inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
72  Atomic32 new_value) {
73  Atomic32 temp, old;
74  __asm__ __volatile__(".set push\n"
75  ".set noreorder\n"
76  "1:\n"
77  "ll %1, %2\n" // old = *ptr
78  "move %0, %3\n" // temp = new_value
79  "sc %0, %2\n" // *ptr = temp (with atomic check)
80  "beqz %0, 1b\n" // start again on atomic error
81  "nop\n" // delay slot nop
82  ".set pop\n"
83  : "=&r" (temp), "=&r" (old), "=m" (*ptr)
84  : "r" (new_value), "m" (*ptr)
85  : "memory");
86 
87  return old;
88 }
89 
90 // Atomically increment *ptr by "increment". Returns the new value of
91 // *ptr with the increment applied. This routine implies no memory barriers.
92 inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
93  Atomic32 increment) {
94  Atomic32 temp, temp2;
95 
96  __asm__ __volatile__(".set push\n"
97  ".set noreorder\n"
98  "1:\n"
99  "ll %0, %2\n" // temp = *ptr
100  "addu %1, %0, %3\n" // temp2 = temp + increment
101  "sc %1, %2\n" // *ptr = temp2 (with atomic check)
102  "beqz %1, 1b\n" // start again on atomic error
103  "addu %1, %0, %3\n" // temp2 = temp + increment
104  ".set pop\n"
105  : "=&r" (temp), "=&r" (temp2), "=m" (*ptr)
106  : "Ir" (increment), "m" (*ptr)
107  : "memory");
108  // temp2 now holds the final value.
109  return temp2;
110 }
111 
112 inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
113  Atomic32 increment) {
115  Atomic32 res = NoBarrier_AtomicIncrement(ptr, increment);
117  return res;
118 }
119 
120 // "Acquire" operations
121 // ensure that no later memory access can be reordered ahead of the operation.
122 // "Release" operations ensure that no previous memory access can be reordered
123 // after the operation. "Barrier" operations have both "Acquire" and "Release"
124 // semantics. A MemoryBarrier() has "Barrier" semantics, but does no memory
125 // access.
126 inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
127  Atomic32 old_value,
128  Atomic32 new_value) {
130  Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
132  return res;
133 }
134 
135 inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
136  Atomic32 old_value,
137  Atomic32 new_value) {
139  Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
141  return res;
142 }
143 
144 inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
145  *ptr = value;
146 }
147 
148 inline void MemoryBarrier() {
149  __asm__ __volatile__("sync" : : : "memory");
150 }
151 
152 inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
153  *ptr = value;
154  MemoryBarrier();
155 }
156 
157 inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
158  MemoryBarrier();
159  *ptr = value;
160 }
161 
162 inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
163  return *ptr;
164 }
165 
166 inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
167  Atomic32 value = *ptr;
168  MemoryBarrier();
169  return value;
170 }
171 
172 inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
173  MemoryBarrier();
174  return *ptr;
175 }
176 
177 } } // namespace v8::internal
178 
179 #undef ATOMICOPS_COMPILER_BARRIER
180 
181 #endif // V8_ATOMICOPS_INTERNALS_MIPS_GCC_H_
void Acquire_Store(volatile Atomic32 *ptr, Atomic32 value)
Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32 *ptr, Atomic32 old_value, Atomic32 new_value)
#define ATOMICOPS_COMPILER_BARRIER()
Atomic32 Release_CompareAndSwap(volatile Atomic32 *ptr, Atomic32 old_value, Atomic32 new_value)
void NoBarrier_Store(volatile Atomic32 *ptr, Atomic32 value)
Atomic32 NoBarrier_AtomicExchange(volatile Atomic32 *ptr, Atomic32 new_value)
Atomic32 Release_Load(volatile const Atomic32 *ptr)
Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32 *ptr, Atomic32 increment)
void Release_Store(volatile Atomic32 *ptr, Atomic32 value)
Atomic32 Barrier_AtomicIncrement(volatile Atomic32 *ptr, Atomic32 increment)
Atomic32 NoBarrier_Load(volatile const Atomic32 *ptr)
Atomic32 Acquire_Load(volatile const Atomic32 *ptr)
int32_t Atomic32
Definition: atomicops.h:57
Atomic32 Acquire_CompareAndSwap(volatile Atomic32 *ptr, Atomic32 old_value, Atomic32 new_value)