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| #define | CALL_GENERATED_CODE(entry, p0, p1, p2, p3, p4) entry(p0, p1, p2, p3, p4) |
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| #define | CALL_GENERATED_REGEXP_CODE(entry, p0, p1, p2, p3, p4, p5, p6, p7, p8) |
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| #define | TRY_CATCH_FROM_ADDRESS(try_catch_address) reinterpret_cast<TryCatch*>(try_catch_address) |
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| #define | GENERATED_CODE_STACK_LIMIT(limit) |
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| typedef int(* | mips_regexp_matcher )(String *, int, const byte *, const byte *, void *, int *, int, Address, int, Isolate *) |
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| #define CALL_GENERATED_CODE |
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| entry(p0, p1, p2, p3, p4) |
| #define CALL_GENERATED_REGEXP_CODE |
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Value:(FUNCTION_CAST<mips_regexp_matcher>(entry)( \
activate correct semantics for inheriting readonliness enable harmony semantics for typeof enable harmony enable harmony proxies enable all harmony harmony_scoping harmony_proxies harmony_scoping tracks arrays with only smi values automatically unbox arrays of doubles use crankshaft use hydrogen range analysis use hydrogen global value numbering use function inlining maximum number of AST nodes considered for a single inlining loop invariant code motion print statistics for hydrogen trace generated IR for specified phases trace register allocator trace range analysis trace representation types environment for every instruction put a break point before deoptimizing polymorphic inlining perform array bounds checks elimination use dead code elimination trace on stack replacement optimize closures cache optimized code for closures functions with arguments object loop weight for representation inference allow uint32 values on optimize frames if they are used only in safe operations track parallel recompilation enable all profiler experiments number of stack frames inspected by the profiler call recompile stub directly when self optimizing trigger profiler ticks based on counting instead of timing weight back edges by jump distance for interrupt triggering percentage of ICs that must have type info to allow optimization watch_ic_patching retry_self_opt interrupt_at_exit extra verbose compilation tracing generate extra emit comments in code disassembly enable use of SSE3 instructions if available enable use of CMOV instruction if available enable use of SAHF instruction if enable use of VFP3 instructions if available this implies enabling ARMv7 and VFP2 enable use of VFP2 instructions if available enable use of SDIV and UDIV instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of MIPS FPU instructions if NULL
Definition at line 60 of file simulator-mips.h.
| #define GENERATED_CODE_STACK_LIMIT |
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Value:(reinterpret_cast<uintptr_t>(this) >= limit ? \
reinterpret_cast<uintptr_t>(this) - limit : 0)
Definition at line 92 of file simulator-mips.h.
| #define TRY_CATCH_FROM_ADDRESS |
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try_catch_address | ) |
reinterpret_cast<TryCatch*>(try_catch_address) |
1.8.6 
