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constants-arm.cc
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27 
28 #include "v8.h"
29 
30 #if defined(V8_TARGET_ARCH_ARM)
31 
32 #include "constants-arm.h"
33 
34 
35 namespace v8 {
36 namespace internal {
37 
38 double Instruction::DoubleImmedVmov() const {
39  // Reconstruct a double from the immediate encoded in the vmov instruction.
40  //
41  // instruction: [xxxxxxxx,xxxxabcd,xxxxxxxx,xxxxefgh]
42  // double: [aBbbbbbb,bbcdefgh,00000000,00000000,
43  // 00000000,00000000,00000000,00000000]
44  //
45  // where B = ~b. Only the high 16 bits are affected.
46  uint64_t high16;
47  high16 = (Bits(17, 16) << 4) | Bits(3, 0); // xxxxxxxx,xxcdefgh.
48  high16 |= (0xff * Bit(18)) << 6; // xxbbbbbb,bbxxxxxx.
49  high16 |= (Bit(18) ^ 1) << 14; // xBxxxxxx,xxxxxxxx.
50  high16 |= Bit(19) << 15; // axxxxxxx,xxxxxxxx.
51 
52  uint64_t imm = high16 << 48;
53  double d;
54  memcpy(&d, &imm, 8);
55  return d;
56 }
57 
58 
59 // These register names are defined in a way to match the native disassembler
60 // formatting. See for example the command "objdump -d <binary file>".
61 const char* Registers::names_[kNumRegisters] = {
62  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
63  "r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc",
64 };
65 
66 
67 // List of alias names which can be used when referring to ARM registers.
68 const Registers::RegisterAlias Registers::aliases_[] = {
69  {10, "sl"},
70  {11, "r11"},
71  {12, "r12"},
72  {13, "r13"},
73  {14, "r14"},
74  {15, "r15"},
75  {kNoRegister, NULL}
76 };
77 
78 
79 const char* Registers::Name(int reg) {
80  const char* result;
81  if ((0 <= reg) && (reg < kNumRegisters)) {
82  result = names_[reg];
83  } else {
84  result = "noreg";
85  }
86  return result;
87 }
88 
89 
90 // Support for VFP registers s0 to s31 (d0 to d15).
91 // Note that "sN:sM" is the same as "dN/2"
92 // These register names are defined in a way to match the native disassembler
93 // formatting. See for example the command "objdump -d <binary file>".
94 const char* VFPRegisters::names_[kNumVFPRegisters] = {
95  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
96  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
97  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
98  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
99  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
100  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15"
101 };
102 
103 
104 const char* VFPRegisters::Name(int reg, bool is_double) {
105  ASSERT((0 <= reg) && (reg < kNumVFPRegisters));
106  return names_[reg + (is_double ? kNumVFPSingleRegisters : 0)];
107 }
108 
109 
110 int VFPRegisters::Number(const char* name, bool* is_double) {
111  for (int i = 0; i < kNumVFPRegisters; i++) {
112  if (strcmp(names_[i], name) == 0) {
113  if (i < kNumVFPSingleRegisters) {
114  *is_double = false;
115  return i;
116  } else {
117  *is_double = true;
118  return i - kNumVFPSingleRegisters;
119  }
120  }
121  }
122 
123  // No register with the requested name found.
124  return kNoRegister;
125 }
126 
127 
128 int Registers::Number(const char* name) {
129  // Look through the canonical names.
130  for (int i = 0; i < kNumRegisters; i++) {
131  if (strcmp(names_[i], name) == 0) {
132  return i;
133  }
134  }
135 
136  // Look through the alias names.
137  int i = 0;
138  while (aliases_[i].reg != kNoRegister) {
139  if (strcmp(aliases_[i].name, name) == 0) {
140  return aliases_[i].reg;
141  }
142  i++;
143  }
144 
145  // No register with the requested name found.
146  return kNoRegister;
147 }
148 
149 
150 } } // namespace v8::internal
151 
152 #endif // V8_TARGET_ARCH_ARM
const int kNumVFPRegisters
Definition: constants-arm.h:97
const int kNumRegisters
Definition: constants-arm.h:92
static const char * Name(int reg, bool is_double)
static int Number(const char *name, bool *is_double)
#define ASSERT(condition)
Definition: checks.h:270
int Bit(int nr) const
static const char * Name(int reg)
const int kNumVFPSingleRegisters
Definition: constants-arm.h:95
static int Number(const char *name)
double DoubleImmedVmov() const
int Bits(int hi, int lo) const
activate correct semantics for inheriting readonliness enable harmony semantics for typeof enable harmony enable harmony proxies enable all harmony harmony_scoping harmony_proxies harmony_scoping tracks arrays with only smi values automatically unbox arrays of doubles use crankshaft use hydrogen range analysis use hydrogen global value numbering use function inlining maximum number of AST nodes considered for a single inlining loop invariant code motion print statistics for hydrogen trace generated IR for specified phases trace register allocator trace range analysis trace representation types environment for every instruction put a break point before deoptimizing polymorphic inlining perform array bounds checks elimination use dead code elimination trace on stack replacement optimize closures cache optimized code for closures functions with arguments object loop weight for representation inference allow uint32 values on optimize frames if they are used only in safe operations track parallel recompilation enable all profiler experiments number of stack frames inspected by the profiler call recompile stub directly when self optimizing trigger profiler ticks based on counting instead of timing weight back edges by jump distance for interrupt triggering percentage of ICs that must have type info to allow optimization watch_ic_patching retry_self_opt interrupt_at_exit extra verbose compilation tracing generate extra emit comments in code disassembly enable use of SSE3 instructions if available enable use of CMOV instruction if available enable use of SAHF instruction if enable use of VFP3 instructions if available this implies enabling ARMv7 and VFP2 enable use of VFP2 instructions if available enable use of SDIV and UDIV instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of MIPS FPU instructions if NULL
Definition: flags.cc:301
const int kNoRegister