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cpu-arm.cc
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27 
28 // CPU specific code for arm independent of OS goes here.
29 #ifdef __arm__
30 #include <sys/syscall.h> // for cache flushing.
31 #endif
32 
33 #include "v8.h"
34 
35 #if defined(V8_TARGET_ARCH_ARM)
36 
37 #include "cpu.h"
38 #include "macro-assembler.h"
39 #include "simulator.h" // for cache flushing.
40 
41 namespace v8 {
42 namespace internal {
43 
44 void CPU::SetUp() {
46 }
47 
48 
51 }
52 
53 
54 void CPU::FlushICache(void* start, size_t size) {
55  // Nothing to do flushing no instructions.
56  if (size == 0) {
57  return;
58  }
59 
60 #if defined (USE_SIMULATOR)
61  // Not generating ARM instructions for C-code. This means that we are
62  // building an ARM emulator based target. We should notify the simulator
63  // that the Icache was flushed.
64  // None of this code ends up in the snapshot so there are no issues
65  // around whether or not to generate the code when building snapshots.
66  Simulator::FlushICache(Isolate::Current()->simulator_i_cache(), start, size);
67 #else
68  // Ideally, we would call
69  // syscall(__ARM_NR_cacheflush, start,
70  // reinterpret_cast<intptr_t>(start) + size, 0);
71  // however, syscall(int, ...) is not supported on all platforms, especially
72  // not when using EABI, so we call the __ARM_NR_cacheflush syscall directly.
73 
74  register uint32_t beg asm("a1") = reinterpret_cast<uint32_t>(start);
75  register uint32_t end asm("a2") =
76  reinterpret_cast<uint32_t>(start) + size;
77  register uint32_t flg asm("a3") = 0;
78  #if defined (__arm__) && !defined(__thumb__)
79  // __arm__ may be defined in thumb mode.
80  register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
81  asm volatile(
82  "svc 0x0"
83  : "=r" (beg)
84  : "0" (beg), "r" (end), "r" (flg), "r" (scno));
85  #else
86  // r7 is reserved by the EABI in thumb mode.
87  asm volatile(
88  "@ Enter ARM Mode \n\t"
89  "adr r3, 1f \n\t"
90  "bx r3 \n\t"
91  ".ALIGN 4 \n\t"
92  ".ARM \n"
93  "1: push {r7} \n\t"
94  "mov r7, %4 \n\t"
95  "svc 0x0 \n\t"
96  "pop {r7} \n\t"
97  "@ Enter THUMB Mode\n\t"
98  "adr r3, 2f+1 \n\t"
99  "bx r3 \n\t"
100  ".THUMB \n"
101  "2: \n\t"
102  : "=r" (beg)
103  : "0" (beg), "r" (end), "r" (flg), "r" (__ARM_NR_cacheflush)
104  : "r3");
105  #endif
106 #endif
107 }
108 
109 
110 void CPU::DebugBreak() {
111 #if !defined (__arm__) || !defined(CAN_USE_ARMV5_INSTRUCTIONS)
112  UNIMPLEMENTED(); // when building ARM emulator target
113 #else
114  asm volatile("bkpt 0");
115 #endif
116 }
117 
118 } } // namespace v8::internal
119 
120 #endif // V8_TARGET_ARCH_ARM
static bool IsSupported(CpuFeature f)
static bool SupportsCrankshaft()
#define UNIMPLEMENTED()
Definition: checks.h:48
static void FlushICache(void *start, size_t size)
static void DebugBreak()
static void SetUp()