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gdb-jit.h
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27 
28 #ifndef V8_GDB_JIT_H_
29 #define V8_GDB_JIT_H_
30 
31 #include "allocation.h"
32 
33 //
34 // Basic implementation of GDB JIT Interface client.
35 // GBD JIT Interface is supported in GDB 7.0 and above.
36 // Currently on x64 and ia32 architectures and Linux OS are supported.
37 //
38 
39 #ifdef ENABLE_GDB_JIT_INTERFACE
40 #include "v8.h"
41 #include "factory.h"
42 
43 namespace v8 {
44 namespace internal {
45 
46 class CompilationInfo;
47 
48 #define CODE_TAGS_LIST(V) \
49  V(LOAD_IC) \
50  V(KEYED_LOAD_IC) \
51  V(STORE_IC) \
52  V(KEYED_STORE_IC) \
53  V(CALL_IC) \
54  V(CALL_INITIALIZE) \
55  V(CALL_PRE_MONOMORPHIC) \
56  V(CALL_NORMAL) \
57  V(CALL_MEGAMORPHIC) \
58  V(CALL_MISS) \
59  V(STUB) \
60  V(BUILTIN) \
61  V(SCRIPT) \
62  V(EVAL) \
63  V(FUNCTION)
64 
65 class GDBJITLineInfo : public Malloced {
66  public:
67  GDBJITLineInfo()
68  : pc_info_(10) { }
69 
70  void SetPosition(intptr_t pc, int pos, bool is_statement) {
71  AddPCInfo(PCInfo(pc, pos, is_statement));
72  }
73 
74  struct PCInfo {
75  PCInfo(intptr_t pc, int pos, bool is_statement)
76  : pc_(pc), pos_(pos), is_statement_(is_statement) { }
77 
78  intptr_t pc_;
79  int pos_;
80  bool is_statement_;
81  };
82 
83  List<PCInfo>* pc_info() {
84  return &pc_info_;
85  }
86 
87  private:
88  void AddPCInfo(const PCInfo& pc_info) {
89  pc_info_.Add(pc_info);
90  }
91 
92  List<PCInfo> pc_info_;
93 };
94 
95 
96 class GDBJITInterface: public AllStatic {
97  public:
98  enum CodeTag {
99 #define V(x) x,
100  CODE_TAGS_LIST(V)
101 #undef V
102  TAG_COUNT
103  };
104 
105  static const char* Tag2String(CodeTag tag) {
106  switch (tag) {
107 #define V(x) case x: return #x;
108  CODE_TAGS_LIST(V)
109 #undef V
110  default:
111  return NULL;
112  }
113  }
114 
115  static void AddCode(const char* name,
116  Code* code,
117  CodeTag tag,
118  Script* script,
119  CompilationInfo* info);
120 
121  static void AddCode(Handle<String> name,
122  Handle<Script> script,
123  Handle<Code> code,
124  CompilationInfo* info);
125 
126  static void AddCode(CodeTag tag, String* name, Code* code);
127 
128  static void AddCode(CodeTag tag, const char* name, Code* code);
129 
130  static void AddCode(CodeTag tag, Code* code);
131 
132  static void RemoveCode(Code* code);
133 
134  static void RegisterDetailedLineInfo(Code* code, GDBJITLineInfo* line_info);
135 };
136 
137 #define GDBJIT(action) GDBJITInterface::action
138 
139 } } // namespace v8::internal
140 #else
141 #define GDBJIT(action) ((void) 0)
142 #endif
143 
144 #endif
const Register pc
activate correct semantics for inheriting readonliness enable harmony semantics for typeof enable harmony enable harmony proxies enable all harmony harmony_scoping harmony_proxies harmony_scoping tracks arrays with only smi values automatically unbox arrays of doubles use crankshaft use hydrogen range analysis use hydrogen global value numbering use function inlining maximum number of AST nodes considered for a single inlining loop invariant code motion print statistics for hydrogen trace generated IR for specified phases trace register allocator trace range analysis trace representation types environment for every instruction put a break point before deoptimizing polymorphic inlining perform array bounds checks elimination use dead code elimination trace on stack replacement optimize closures cache optimized code for closures functions with arguments object loop weight for representation inference allow uint32 values on optimize frames if they are used only in safe operations track parallel recompilation enable all profiler experiments number of stack frames inspected by the profiler call recompile stub directly when self optimizing trigger profiler ticks based on counting instead of timing weight back edges by jump distance for interrupt triggering percentage of ICs that must have type info to allow optimization watch_ic_patching retry_self_opt interrupt_at_exit extra verbose compilation tracing generate extra emit comments in code disassembly enable use of SSE3 instructions if available enable use of CMOV instruction if available enable use of SAHF instruction if enable use of VFP3 instructions if available this implies enabling ARMv7 and VFP2 enable use of VFP2 instructions if available enable use of SDIV and UDIV instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of MIPS FPU instructions if NULL
Definition: flags.cc:301
activate correct semantics for inheriting readonliness enable harmony semantics for typeof enable harmony enable harmony proxies enable all harmony harmony_scoping harmony_proxies harmony_scoping tracks arrays with only smi values automatically unbox arrays of doubles use crankshaft use hydrogen range analysis use hydrogen global value numbering use function inlining maximum number of AST nodes considered for a single inlining loop invariant code motion print statistics for hydrogen trace generated IR for specified phases trace register allocator trace range analysis trace representation types environment for every instruction put a break point before deoptimizing polymorphic inlining perform array bounds checks elimination use dead code elimination trace on stack replacement optimize closures cache optimized code for closures functions with arguments object loop weight for representation inference allow uint32 values on optimize frames if they are used only in safe operations track parallel recompilation enable all profiler experiments number of stack frames inspected by the profiler call recompile stub directly when self optimizing trigger profiler ticks based on counting instead of timing weight back edges by jump distance for interrupt triggering percentage of ICs that must have type info to allow optimization watch_ic_patching retry_self_opt interrupt_at_exit extra verbose compilation tracing generate extra code(assertions) for debugging") DEFINE_bool(code_comments